Bio

I have 7+ years experience in the SI/PI domain as a consultant and simulation engineer for (LP)DDR and NAND memory products as well as I/O modeling for high-speed SerDes PHY covering 10G NRZ to 56G PAM4. Expertise in interconnect modelling and timing analysis tools such as SIwave, HFSS, HSPICE, FineSim, ADS. Deep knowledge of EDA’s modelling and simulation technologies. Channel simulator algorithm (PDA, Statistical Analysis), MOR/Macro-Modelling techniques, IBIS-AMI flow, DOE/RSM design optimization. Proficient in using several programming languages such as TCL, Bash, Python. - Familiar with writing post-processing scripts and tools to extract DDR margin data out of large simulation dataset. Experienced in developing channel simulator, and iterative design optimization scripts using TCL Strong analytical skills and experienced MATLAB user, developed and deployed several SI/PI toolbox in PCB and PKG design teams.