Bio

Designing low power digital circuits for VLSI technology. Reduced 24% of dynamic power in clock trees using a novel adiabatic technique that consists of switched capacitors and transmission gates. Used Miller effect to redesign the existing resonant clocking to get 45% dynamic power savings with 10% area savings. Designed and implemented a novel compression algorithm for High Definition video on FPGA, the algorithm reconstructs a 1080p video with 93% of its original quality and 26% compression ratio.