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Mahesh Wagh

Co-Chair CXL Consortium Board Technical Task Force

CXL Consortium

Country or State

United States


I am AMD Sr. Fellow, Server System Architect at AMD Datacenter System Architecture and Engineering team developing world-class products and solutions around EPYC processors. Prior to joining AMD, I was a Senior Principal Engineer at Intel corporation, focusing on IO and SoC architecture and related technology developments. I have a broad experience in chipset and IO architecture, design and validation on both Server and Client platforms. I have a proven track record of driving multiple cross discipline teams from technology concept, technology standards definition through product delivery phases. Some of my significant achievements are the enhancements to PCI Express Architecture and Specification. Leading CPU IO domain architecture and IO IP architecture & Interfaces. Leading Compute Express Link (CXL) Areas of Expertise: Server System Architecture CXL Interfaces: LPIF, PIPE PCI and PCI Express Architecture Coherent Interconnects MIPI M-PHY and associated protocols Accelerators and Inter Processor Communication protocols (IPC) Virtualization SR-IOV Hardware/Software Interfaces SoC & Chipset Architecture definition and development Uarch definition and RTL Design Post & Pre-Silicon Verification FPGA based proof of concept platforms Specification development Patents and Publications • >80 Patents from USPTO in the area of IO Architecture • 30 talks at Industry events, PCI SIG, Intel Developer Forum and WinHEC

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Current Position

Co-Chair CXL Consortium Board Technical Task Force at CXL Consortium


ME, Electrical

Past Talks

DesignCon 2023