Bio

Focus on building and improving on the IP quality checking spanning across all phases in product development and product release. Ownership of the IP release processes across all technology nodes, from 28nm down to 3nm and support of the Silicon Life Management - Hardware Applications Team usage of the process. Managing, maintaining and delivering the IP portfolio of in-chip monitoring process, voltage and temperature (PVT) sensors in all popular process nodes down to 3nm meeting both business and customer expectations. Close co-operation with design teams, CAD, project management, Methodology, Process, Applications, IP vendors and Foundries in integrating selected IP into design environment to enable correct, best-in-class and most efficient usage. Principal IP maintenance contact for in-chip monitoring sensors. Design environment engineer specializing in digital implementation flow from RTL to GDS. Specialties: IP flow; RTL to netlist, IP deliverables, digital IP Re-use Synthesis, Floorplanning, Clock tree synthesis, Place and Route, Timing analysis and verification of complex SOCs using the latest EDA tools in advanced process technologies