Bio

Intel Corporation, Principal Engineer, 2002-present Current: Physical layer (PHY) owner for the USB 3.0 specification with 5 Gb/s SuperSpeed data rates. Past accomplishments: Led R&D of high speed differential signaling technologies for PCs. Identified key technical barriers, solution options, and high level plans for products to be introduced in 5+ years. Developed accurate models with correlation to measurements thru 20 GHz, including surface roughness and dielectric loss mechanisms. Built a team in Guadalajara, Mexico to conduct advanced research. Intel Corporation, Manager, Electrical Platform Technologies, 1998-2002 Managed 25 person team with responsibility for development of interconnect, power delivery, EMI and PCB technology solutions for PCs. Developed solutions for the Rambus DRAM channel, Pentium® 4 Processor frontside bus (FSB), AGP 4x/8x, and DDR II interfaces. Intel Corporation, Staff Hardware Engineer, 1995-1998 Managed team of four engineers that delivered high speed interconnect solutions for the 400 MHz Pentium(r) II Processor L2 bus & 266 MHz AGP bus. Team leader for the 100 MHz Pentium(r) II Processor FSB. Defined & executed project schedules while providing technical direction to an inter-organizational team that developed I/& and interconnect models, system timing specs, & customer design guides. Defined the design process, used it to establish the feasibility of scaling the FSB to 133 MHz, & got multiple Intel design teams to adopt it as the best known method. IBM Corporation, Packaging Development Engineer, 1988-1995 IBM Corporation, Quality Engineer, 1985-1988 Oregon Graduate Institute, Adjunct Professor, 1997-2009 Taught EE564, “High Speed Digital Interconnect,” a graduate class in signal integrity. Defined and developed the course curriculum and materials. Co-author of ''Advanced Signal Integrity for High-Speed Digital Designs,'' a graduate level published by John Wiley & Sons in 2009. Specialties: Signal integrity engineering: printed circuit board technology, I/O circuits, equalization, jitter analysis.