Bio

High Speed IO circuit architect with substantial hand-on experience. Focus on DDR technology, signal integrity optimization. IO path designer with broad experience with clock domain transfer and clocking architecture. Direct experience with Delay Locked loop design, phase interpolator design and other on-clocking design. Inventor of over 37 US patents. IEEE Senior Member Specialties: Power Delivery Network & Noise Analysis On-die variation modeling & compensation techniques DRAM timing protocol optimization